ASIC development within the smart-MEMPHIS project

During Spring 2016 the first generation ASIC developed within the smart-MEMPHIS EU project was received from the ASIC foundry in Austria, AMS. It has since been tested and characterized. The evaluation board was developed to test the variety of harvesting sources and scenarios intended for the smart-MEMPHIS project.

Evaluation board for the smart-MEMPHIS ASIC.

The ASIC consists a series of voltage regulators taking the input power generated by the harvesting device and producing a settled voltage for the rest of the system to operate with. The block diagram of the first-generation ASIC is shown below. We can see how a set of inputs can be selected and dependent on the voltage and power level, the voltages are regulated up or down.

The first-generation ASIC offers a modular design for multiple harvesters, as well as voltage and power levels.

This version of the ASIC is some 5.5 sq mm including two sets of IO interfaces: one for wire bonding and one for flip chip. Wire bonding is used in bench test and flip chip is used in the 3D integration procedure intended for smart-MEMPHIS. Future generations of the ASIC will shrink towards a minimum size in the final generation upon end of the project.

The ASIC is tested with different sets of energy sources. In the bench we use calibrated, commercially available piezo-electric cantilever elements that are excited through a commercial shaker as well as a cheaper shaker developed within the project in order to evaluate and develop a proper test bed for harvesting ultra low power levels.

In the bench tests we typically stress the devices to understand how low input power levels and how high output currents it can withstand. Measured results illustrating the power efficiency captured for different output voltages levels given comparatively high output currents and low input power levels (in the sub uW regime) are shown in the figure below. These results are for the switched-capacitor converter in voltage boosting mode, i.e., increasing the voltage.

Chip plot of the design showing the wire-bond pad frame and voltage converters, rectifiers, and auxiliary circuits within 2.3x2.3 sq mm.

Example bench setup with one of the commercial harvesters used for the tests.

Author(s): Jacob J Wikner, LiU

Posted on September 7, 2016 .